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The Itanium 2 is an IA-64 architecture microprocessor developed jointly by Hewlett-Packard and Intel, introduced on July 8, 2002. It put the architecture back on track and obtained leadership performance in many benchmarks. Impressively for an in-order processor, some two and a half years after its release the Itanium 2 core remains the most efficient processor according to the SPECint2000/GHz (http://www.aceshardware.com/SPECmine/index.jsp?b=0&s=3&v=2&if=0&ncf=1&nct=256&cpcf=1&cpct=2&mf=250&mt=3800&o=0&o=1) and SPECfp2000/GHz (http://www.aceshardware.com/SPECmine/index.jsp?b=2&s=3&v=2&if=0&ncf=1&nct=256&cpcf=1&cpct=2&mf=250&mt=3800&o=0&o=1) metrics. It also has the highest outright SPECfp2000 (http://www.aceshardware.com/SPECmine/index.jsp?b=2&s=1&v=2&if=0&ncf=1&nct=256&cpcf=1&cpct=2&mf=250&mt=3800&o=0&o=1) result.
All Itanium 2 processors to date share a common cache hierarchy. They have 16k of Level 1 instruction cache and 16k of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256k. The Level 3 cache is also unified and varies in size from 1.5MB to 9MB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU.
The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200MHz, 128-bit wide, double pumped bus capable of 6.4GB/s -- more than three times the bandwidth of the Merced bus. In 2004, Intel released processors with a 266MHz bus, increasing bandwidth to 8.5GB/s. Rumour has it that 2005 will see a 333MHz bus.
The future of the Itanium family apparently lies in multi-core chips, as the available information about coming generations like Montecito/Montvale and Tukwila (those are internal code names; the final products will most likely also bear the Itanium brand) shows.
McKinley
McKinley was the first version of Itanium 2, manufactured in an 0.18µm process. It was released at speeds of 900MHz
and 1GHz, with cache sizes of 1.5MB and 3MB. It added the branchlong instruction to the IA-64 instruction set. IA-32 performance, while improved, was still much slower than that of current x86 processors; McKinley's x86 performance was similar to that of a Pentium II at 2/3 the clock speed.
Madison
Madison was initially introduced on June 30, 2003. It was initially available in three versions: 1.3GHz with 3MB of cache, 1.4GHz with 4MB of cache and 1.5GHz with 6MB of cache. Manufactured in an 0.13µm process, it had a die size of 374mm². Its power envelope remained unchanged from McKinley at 130 Watts. On September 8, 2003, a 1.4GHz version with 1.5MB of cache was released. A 1.6GHz version with 6MB of cache and a 1.4GHz version with 3MB of cache were launched on April 13, 2004. November 8, 2004 saw the release of a 1.6GHz version with 9MB cache.
Hondo
Hondo was announced as the HP mx2 dual-processor module on February 18, 2003 and started shipping in early 2004. It consists of two Madison cores with 32MB of L4 cache and fits in the same space as a normal Itanium 2 CPU. It is only available from HP. Currently the cores run at 1.1GHz with 4MB L3 cache each.
Deerfield
Deerfield was released on September 8, 2003. With 1.5MB of cache, running at 1GHz, this was the first Low Voltage Itanium processor. Its 62 Watt power envelope made it more suited for blade and 1U servers.
Fanwood
The Fanwood core debuted on November 8, 2004. Versions include a 1.6GHz edition with 3MB of L3 cache with either 200MHz or 266MHz FSB and a Low Voltage 1.3GHz version with 3MB L3 cache at 200MHz.
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