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Montecito is an unincorporated town in Santa Barbara County, California. See Montecito, California.
Montecito is the code-name of the next major release of Intel's Itanium Processor Family (IPF), which implements the IA-64 instruction set architecture:
Expected Features and Attributes:
- 2-way coarse-grained multithreading per core (not simultaneous), a total of 4 threads per die
- seperate 1 MB Instruction L2 and 256 KB Data L2 per core, improved hierarchy
- More than 1.7 billion transistors per die, of which more than 1.4 billion is made up by the 24 MB L3 cache
- Die size likely to be 580 mm2 approx.
- Likely more conservative frequency, around 1.6 GHz clock speed, than earlier expected. This is an issue due to the transistor count, die size (clock distribution), and thermal dissipation.
- Advanced clock scaling technology for power management -- the clock rate is not fixed, but adjusted to the thermal envelope, what means that under some usage patterns the chip will scale down, while under other cases it will be able to scale up clock speed (Foxton technology)
- Lower power consumption than earlier flagship Itaniums (100 W has been suggested)
- Advanced compensation for errors in cache (Pellston technology)
- Virtualization technology allowing multiple OS instances per chip (Silvervale)
- Improved, higher bandwidth FSB, with three times the capacity of the existing bus design. What we don't know yet is whether it meant to be at device level (per die) or at system level (per node, with 4 dies). System throughput per node will be at least 21 Gbytes per second.
- Will also be avaliable with legacy FSB for upgrading existing system designs
- 90 nm process with 65 nm shrink planned (shrink codenamed Montvale)
- Under evaluation by major OEMs
- Commercial launch: 2005 H2
- Volume: 2006
Montecito is also the name of the fictional hotel in the NBC television series Las Vegas.
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