|
One of the major improvements Peripheral Component Interconnect (PCI) had over other I/O architectures was its configuration mechanism. In addition to the normal memory-mapped and port spaces, it has configuration space. This is 256 bytes that is addressable by knowing the PCI bus, device and function numbers for the device. The first 64 bytes of configuration space are standardised; the remainder are avilable for vendor-defined purposes.
In order to allow more parts of configuration space to be standardised without conflicting with existing uses, there is a list of capabilities.
Each capability has one byte that describes which capability it is, and one byte to point to the next capability. The number of additional bytes depends on the capability ID.
PCI-X 2.0 and PCI Express introduced an extended configuration space, up to 4096 bytes. The only standardised part of extended configuration space
is the first 4 bytes at 0x100 which are the start of an extended capability list. Extended capabilities are very much like normal capabilities except that they can refer to any byte in the extended configuration space (by using 12 bits instead of 8), have a 4-bit version number and a 16-bit capability ID. Extended capability IDs overlap with normal capability IDs, but there is no chance of confusion as they are in separate lists.
Standardised registers
The Vendor ID and Device ID registers identify the device, and are commonly called the PCI ID. The 16-bit vendor ID is allocated by the PCI SIG. The 16-bit device ID is then assigned by the vendor. There is an ongoing project to collect all known Vendor and Device IDs. (See #external links.)
The Subsystem Vendor ID and the Subsystem Device ID further identify the device. The Vendor ID is that of the chip manufacturer, and the Subsystem Vendor ID is that of the card manufacturer. The Subsystem Device ID is assigned by the subsystem vendor, but is assigned from the same number space as the Device ID.
The Command register contains a bitmask of features that can be individually enabled and disabled.
The Status register is used to report which features are supported and whether certain kinds of error have occurred.
The Cache Line Size register must be programmed before the device is told it can use the memory-write-and-invalidate transaction. This should normally match the CPU's cache line size, but the correct setting is system dependent.
In order to address a device through port space or memory space, system firmware or the OS will program the Base Address Registers (commonly called BARs). Each non-bridge device can implement up to 6 BARs, each of which can respond to certain areas of port or memory space.
A device can have a ROM.
External link
| 
