PowerPC G4 - Definition

The PowerPC G4 is a RISC-based microprocessor belonging to the PowerPC family of processors. It is used in Apple Macintosh computers such as the PowerBook G4, the iMac G4, the eMac, the Mac mini, the 3rd generation iBook, and the desktop Power Macintosh G4.

Most of the G4 design was done by Motorola in close cooperation with Apple. The name is a designation given by Apple indicating that the design is of the "fourth generation" of PowerPC architectures. IBM, the third member of the AIM alliance, chose not to participate in the design of the G4 in part owing to microprocessor design disagreements concerning a Vector Processing Unit on the chip. Ultimately, the G4 architecture design contained a 128-bit vector processing unit called AltiVec (also known as "Velocity Engine" in Apple's marketing literature).

Description

With the AltiVec unit, the G4 microprocessor can do four-way single precision floating point math, or 16-way byte math in a single cycle. Furthermore, the vector processing unit on the G4 is superscalar, and can do two vector operations at the same time. Compared to Intel's x86 microprocessors at the time, this feature offered a substantial performance boost to applications designed to take advantage of the AltiVec unit.

Additionally, Motorola designed the G4 with enhanced support for symmetric multiprocessing (SMP). The G3 microprocessor line had some support for SMP, but computers using G3s in the SMP role took performance hits. By contrast, the G4 supports not only multi-processing, but also allows G4s used in SMP computers to pass data chip-to-chip in an extremely efficient manner.

Another big performance boost in the G4 microprocessor came from a 64-bit ALU, derived in part from the 604 series ALU. The 603 and G3 series had 32-bit ALUs, which took two clock cycles to accomplish 64-bit floating point arithmetic.

The FPU in the G4 was also taken from the 604 CPU, because it was roughly 25% faster per clock than the FPU in the G3; originally, the G3 was intended to be a step down from Apple's 604ev (MACH IV) CPU, but when they realized how fast it was with the fast backside L2 SRAM cache, they decided to scrap the PPC604ev, and stick with the PPC750 (G3).

Production

The first version of the G4 microprocessor line was called the MPC 7400. It debuted in late summer of 1999 at speeds ranging from 350 to 500 MHz. The chip contained 10.5 million transistors and was manufactured using Motorola's 0.20 μm HiPerMOS6 process. The chip die measured 83 mm2 and featured copper interconnects.

Motorola's inability in 1999 to obtain yields of the G4 line at Apple's desired clock speed caused Apple to do an abrupt about-face on sales of its Power Macintosh G4 tower series of computers. The PowerMac series was downgraded abruptly from 400, 450, and 500 MHz processor speeds, to 350, 400, and 450 MHz. The incident caused a rift in the Apple-Motorola relationship, and reportedly caused Apple to ask IBM for assistance to get the production yields up on the Motorola G4 line.

The 1999 problems foreshadowed difficulities Motorola and Apple faced in competing with Wintel-x86 system clock speed increases, and the "Megahertz Myth." It also perhaps ultimately caused Apple to release SMP versions of the Power Mac G4 series (with the ad campaign "Two brains are better than one") to make up for a perceived gap in performance between the Power Mac line, and competing x86-based systems running at higher microprocessor clock speeds.

G4 variants

As of early 2005, the fastest clocked G4 processor shipping in Apple's G4 lineup is the MPC 7447B, running at 1.67 GHz (in the new Powerbooks). Apple is phasing out the G4 (Freescale, spun off from Motorola in 2004, has faster G4 chips - the 7448 and the rumored 7447B¹ - but Apple has given no indication it plans to utilise them) in favor of the 64-bit IBM-produced PowerPC 970, and possibly the planned Freescale-produced system-on-a-chip (SoC) PowerPC variant (Apple famously does not comment on future products, and rarely publishes which chips it uses or intends to use). SMP and Altivec, however, did correct for the deficiency in the G4's platform bandwidth. While only a 167MHz FSB, the width of the bus was such that the vector units (which processed Altivec) were never starved for data as some have erroneously claimed. Furthermore, this issue could only have happened in a situation where one was running a pure Altivec code mix, so, even if the bus had not provided sufficient bandwidth, the top end would never have been reached in a real world situation. At one point, there was speculation of the "legendary" PPC7470 which would have fixed this, but it never came to pass.

The problems associated with the bandwidth constrained G4 MPX bus interface are believed to be relieved with Freescale's proposed line of SoC devices, sporting an option for a faster system interface via a RapidIO or PCI-Express, and an onboard DDR memory controller. This architecure, however, is still pre-production as of 1Q2005.