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Term referring to a CPU architecture which further divides each of the traditional pipeline stages (see Pipeline_(computer), Classic RISC pipeline) to obtain improved thruput and higher clock rates.
The design does have its drawbacks, however. A superpipelined architecture will experience a performance hit whenever the pipeline isn't full, in the same way extra time is needed before the first car makes it through all the stages and comes off the assembly line. Whenever the processor's branch predictor fails to predict a branch instruction in a program, the pipeline gets flushed out while a (comparatively) slow read from random access memory into the processor cache takes place. From that point, the number of clock cycles for the first instruction to finish is equal to the number of stages in the pipeline. This has led some to criticize this design practice where they feel it has been taken to the extreme, such as on Intel's Prescott core, rumored to have somewhere around 30 stages.
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--66.26.155.103 03:55, 5 Jan 2005 (UTC)
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