IEEE 1076 (1451 bytes)
1: ... [[VHSIC]] [[Hardware Description Language]] or [[VHDL]]. It was originally developed by CLSI under cont...
14: * [[IEEE 1076.1]] VHDL Analog and Mixed-Signal
15: * [[IEEE 1076.1.1]] VHDL-AMS Standard Packages (stdpkgs)
16: * [[IEEE 1076.2]] VHDL Math Package (math)
17: * [[IEEE 1076.3]] VHDL Synthesis Package (vhdlsynth)

Modelica (1072 bytes)
6: ...and mixed-signal behavior). Most applications of VHDL-AMS and Verilog-AMS involve electrical systems bu...

SystemC (1774 bytes)
1: ... of as a ''hardware description language'' like [[VHDL]] and [[Verilog]], but is more aptly described as...
5: ...nel is not to be compared with that of commercial VHDL/Verilog simulators at the present.

VHSIC (356 bytes)
1: ...in a project that led to the development of the [[VHDL]] language.

Property Specification Language (424 bytes)
1: ...are]] designs. It comes in two flavors, one for [[VHDL]] and one for [[Verilog]].

VHSIC hardware description language (6600 bytes)
1: '''VHDL''' or [[VHSIC|'''V'''HSIC]] [[Hardware descriptio...
5: VHDL was originally developed at the behest of the [[U...
6: ...nies were including in equipment. That is to say, VHDL was developed as an alternative to huge, complex ...
8: ...scendant of [[Algol_programming_language|Algol]]. VHDL is [[Case sensitivity|case insensitive]].
10: ...ording to what the user specifies. Thus, the same VHDL code could be synthesized differently for lowest ...

Accellera (402 bytes)
2: [[VHDL International]]. '''Accellera''' is a [[standards...

Logic synthesis (727 bytes)
1: ...Hardware Description Language|HDL]]s, including [[VHDL]] and [[Verilog]]. Some tools can generate bitst...

Schematic editor (1036 bytes)
13: ... to input designs from various formats, such as [[VHDL]], [[Verilog]], [[EDIF]].

Design Compiler (1124 bytes)
1: ...stricted sub-languages of either [[Verilog]] or [[VHDL]], into a [[gate-level]] [[netlist]] representati...

IEEE 1164 (1273 bytes)
1: ... a uniform representation of a logic value in a [[VHDL]] hardware description. The standardization effor...

OpenCores (1425 bytes)
3: ...hardware description language]]s [[Verilog]] or [[VHDL]], which may be synthesized to either silicon or ...

Entity (1978 bytes)
19: * In [[VHDL]], '''entity''' is the keyword for defining a new...

ABEL programming language (1584 bytes)
7: ...[[Hardware description language|HDLs]]) such as [[VHDL]] and [[Verilog]] have gained in popularity. None...

Xilinx (1798 bytes)
10: ...S such as [[Linux]] and interfacing with custom [[VHDL]] logic.

Electronics related books (2080 bytes)
8: * ''A VHDL Primer'' by [[J. Bhaskar]] Pub::[[Pearson Educati...

Hardware description language (6265 bytes)
28: *'''[[VHDL]]'''
38: ...etary HDLs and towards the two leading standards, VHDL and Verilog HDL.

Synopsys (2391 bytes)
5: ...e and route]] [[software]], and [[Verilog]] and [[VHDL]] simulators. The simulators include a powerful ...

Zilog Z80 (5654 bytes)
27: ...s.org/projects.cgi/web/tv80/overview] source. The VHDL version, once synthesized, can be clocked up to 3...

Cadence Design Systems (2721 bytes)
11: ...and [[functional verification]] of [[Verilog]], [[VHDL]], and [[SystemC]] netlists. Also includes hardw...

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